1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly relates to a semiconductor memory device in which a transistor having a read gate construction is connected between a bit line and a data bus.
2. Description of the Related Art
In the related art, a semiconductor memory device which stores data read and written as an electrical signal (voltage), for example, as shown in FIG. 1, has been comprised of a sense amplifier 32 which amplifies and outputs a voltage read from a memory cell (not illustrated) to a bit line 30 and an inverted bit line 31 at the time of a read operation, and supplies a write voltage via the bit line 30 and the inverted bit line 31 to the memory cell at the time of a write operation; read/write data buses 33 and 34 which output the read voltage at the time of a read operation, and receive as their inputs the write voltage at the time of a write operation; and transfer gates 35 and 36 which perform the switching of the above-described sense amplifier 32 and the read/write data buses 33 and 34.
In the semiconductor memory device shown in FIG. 1, the read operation of data is carried out by reading out the data stored in the memory cell to the bit line 30 and the inverted bit line 31 as the read voltage, amplifying this read voltage by the sense amplifier 32, and supplying this via the transfer gates 35 and 36 to the read/write data buses 33 and 34. The write operation of data is carried out by supplying the write voltage from the read/write data buses 33 and 34 via the transfer gates 35 and 36 to the sense amplifier 32 and supplying this write voltage via the bit line 30 and the inverted bit line 31 to the memory cell.
The above-mentioned semiconductor memory device shown in FIG. 1 has a problem, however, in that, since the capacitances of the read/write data buses 33 and 34 are added to the bit line 30 and the inverted bit line 31 and the capacitance of the memory cell is generally small, the read voltage is slow in rising and therefore a high speed operation is difficult.
FIG. 2 is a view of an example of the configuration of a semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. 61-123093 adopting this method. This device is an example in which the bit lines of each row are divided into a plurality of lines.
In the figure, BLi0, .sub.-- BLi0, BLi1, .sub.-- BLi1, . . . denote a plurality of divided bit line pairs of an i-th row comprising a bit line and an inverted bit line (.sub.-- indicates inversion); WL00 to WL0n, WL10 to WL1n, . . . denote word lines; C00 to C0n, C10 to C1n, . . . denote memory cells belonging to the same row; PRE0, PRE1, . . . denote precharge circuits; SA0, SA1, . . . denote sense amplifiers; BK0, BK1, . . . denote divided blocks (memory arrays); Si0.sub.A :Si0.sub.B, Si1.sub.A :Si1.sub.B, . . . denote switch circuits which serially connect the bit lines of the block or release the same; Q1 and Q2 denote transfer gates controlled by a column selection signal Y; and DB and .sub.-- DB denote data buses.
The memory cells C00 to C0n are connected to the bit line pair BLi0 and .sub.-- BLi0, and the memory cells C10 to C1n are connected to the bit line pair BLi1 and .sub.-- BLi1. They are divided into blocks of BK0 and BL1.
The blocks BK0, BK1, . . . are provided with sense amplifiers SA0, SA1, . . . , respectively, which sense amplifiers SA0, SA1, . . . are activated by block selection signals BS0, BS1, . . .
FIGS. 3A to 3E are views giving detailed examples of the configuration of different portions of the device, wherein FIG. 3A shows a bit line precharge circuit PRE; FIG. 3B and FIG. 3C show switch circuits Si for connecting the bit line; and FIG. 3D and FIG. 3E show examples of the configuration of the sense amplifier 3A.
The precharge circuit PRE0, as shown in FIG. 3A, is comprised of N-channel MOS transistors Q3 to Q5 with gates connected to the supply line of the precharge signal P. The sources of the precharge transistors Q3 and Q4 are connected to the supply line of the power source voltage (1/2)V.sub.cc. An equalizing transistor Q5 is connected between the drains of the two transistors Q3 and Q4 connected to the bit line pair BLi0 and .sub.-- BLi0.
The precharge circuit PRE0 of this configuration precharges the bit lines BLi0 and .sub.-- BLi0 to the same potential (1/2V.sub.cc -V.sub.1b) when the precharge signal P is given. The same applies to the precharge circuits PRE1 . . . of other blocks.
The switch circuit Si shown in FIG. 3B comprises an N-channel MOS transistor Q6, while the switch circuit Si shown in FIG. 3C is constituted by connecting sources and drains of the transistor Q6 and a P-channel MOS transistor Q7 having an inverse conductivity to that of the transistor Q6.
The switch circuit Si shown in FIG. 3B is made conductive by inputting a clock signal .phi.1 to the gate of the transistor Q6.
The switch circuit Si shown in FIG. 3C simultaneously makes both of the transistors Q6 and Q7 conductive by supplying a clock signal .phi.1 and an inverse clock signal .sub.-- .phi.1 thereof of complementary levels to the gates of the transistors Q6 and Q7.
The sense amplifier SA shown in FIG. 3D comprises N-channel MOS transistors Q8 and Q9 with sources connected to the supply line of the signal BS0. The gate of the transistor Q9 and the drain of the transistor Q8 are connected to the bit line BLi0, and the gate of the transistor Q8 and the drain of the transistor Q9 are connected to the inverted bit line .sub.-- BLi0.
The sense amplifier SA shown in FIG. 3E has a so-called flip-flop structure of cross-connected CMOS inverters in which the drains of the P-channel MOS transistors Q10 and Q11 with sources connected to the supply line of the inverted signal .sub.-- BS0 are connected to the drains of the transistors Q8 and Q9 of the sense amplifier SA shown in FIG. 3D, respectively.
Both of the sense amplifiers latch data of complementary levels of the bit line pair BLi0 and .sub.-- BLi0 and amplify the same.
In a semiconductor memory device having such a configuration, one line among the word lines WL00 to WL0n of the block BK0 is selected. When the i-th row of cells belonging to this word line is selected, only the sense amplifier SA0 is activated by the block selection signal BS0.
As a result, the differential voltage between the bit lines BLi0 and .sub.-- BLi0 is enlarged at the sense amplifier SA0, and all switch circuits Si0.sub.A :Si0.sub.B, Si1.sub.A :Si1.sub.B, . . . are held in the conductive state.
Due to this, the bit lines BLi0, .sub.-- BLi0, BLi1 and .sub.-- BLi1 are connected in series. Also, the column selection signal Y is supplied to the gates of the transistors Q1 and Q2 at a high level and the gates Q1 and Q2 are controlled to the conductive state, the bit line pair is connected to the data buses DB and .sub.-- DB, and the data is read onto the data buses DB and .sub.-- DB.
The advantage of the bit line division mentioned above is that the load capacitance of each sense amplifier at the time of a sense operation is small, that is, a load capacitance of only one set of the divided bit line pair is sufficient.
However, in the above-mentioned semiconductor memory device, when the switch circuits Si0.sub.A :Si0.sub.B, Si1.sub.A :Si1.sub.B, . . . are made conductive to connect the bit line pairs, the load capacitance of the sense amplifier is increased to the value before the division of the bit lines. For this reason, the once amplified voltage on the bit line pair is reduced and the driving ability of the sense amplifier is impaired. In the end, the time until a required differential voltage is produced on the data buses DB and .sub.-- DB is not shortened much at all.